The present invention relates to a digital PLL circuit for use in a digital synthesizer or the like. Description of the Related Arts
In a conventional digital PLL (phase-locked loop) circuit, a phase comparison is carried out at a zero cross point.
In FIG. 1 there is shown a conventional digital PLL circuit. The digital PLL circuit is comprised of a sampling circuit 7 for sampling input signals I, a discrimination circuit 8 for comparing an output value of the sampling circuit 7 with a predetermined threshold value T to generate a control signal C, a loop filter 9 for smoothing the control signal C output from the discriminating circuit 8 to output a smoothed control signal CS, a VCO (voltage-controlled oscillator) 6 controlled by the smoothed control signal CS output from the loop filter 9, a zero cross detection circuit 10 for detecting the zero cross point of the input signal I to output an enable signal E, and a reference signal generating circuit 5 set by the enable signal E to generate a timing signal TK to the sampling circuit 7 in synchronism with an output signal O of the VCO 6.
Next, the operation of the conventional digital PLL circuit will now be described in connection with FIG. 2.
FIG. 2 is a timing chart showing an operation of the conventional digital PLL circuit shown in FIG. 1. First, an input signal I of a sine wave signal given an A/D (analog-digital) conversion is input from an input terminal TI, and the input signal I is applied to the sampling circuit 7 and the zero cross detection circuit 10.
Next, the zero cross detection circuit 10 detects the zero cross point of the input signal I and outputs an enable signal E rising at a timing of the detection of the first zero cross signal Z1 to the reference signal generating circuit 5. This enable signal E, for example, can be generated by an RS (reset-set) flip-flop using the zero cross signal as a set signal.
Then, the reference signal generating circuit 5 inputs the output signal O of the VCO 6 at a timing of the setting of the enable signal E and outputs the timing signal TK whose frequency is synchronized with the output signal O.
In the sampling circuit 7, this timing signal TK is input as a sampling timing signal to carry out the sampling of the input signal I to output sample values S (S1 to S4).
Next, in the discrimination circuit 8, each sample value S is compared with a predetermined threshold value T to output a control signal C for the VCO 6. In this case, the threshold value T is either a positive threshold value TP or a negative threshold value TN with respect to the central value TO. For instance, as shown in FIG. 2, when the sample value S4 sampled by the positive threshold value TP is large, it is discriminated that the phase of the output signal O of the VCO 6 is lagged compared with the input signal I, and a control signal C for raising the frequency is output to the VCO 6. On the contrary, when the sample value 3 sampled by the negative threshold value TN is small, it is discriminated that the phase of the output signal O of the VCO 6 is led compared with the input signal I, and a control signal C for dropping the frequency is output to the VCO 6. Further, in case of the sample value S2 positioned between the positive threshold value TP and the negative threshold value TN, it is discriminated that the phase of the output signal O of the VCO 6 is equal to the input signal I, and a control signal C for maintaining the frequency is output to the VCO 6. Alternatively, in case of a VCO for holding the frequency when no control signal is input, the output of the control signal C is stopped. As described above, the discrimination circuit 8 controls the VCO 6 so that the sample value S obtained by sampling the input signal I in the sampling circuit 7 may be within a range between the positive threshold value TP and the negative threshold value TN.
Next, the output of the discrimination circuit 8 is smoothed in the loop filter 9 to output a smoothed control signal CS to the VCO 6. The VCO 6 is controlled by the smoothed control signal CS to output an output signal O having a predetermined frequency range as an output signal of the digital PLL circuit to an output terminal TO.
In the above-described conventional digital PLL circuit, when the value of the A/D-converted input signal is largely varied near the zero cross and the input signal is accompanied with an amplitude variation in particular, since the value near the zero cross is further increased, the variation of the output signal of the discrimination circuit becomes large and, even when the smoothing in the loop filter is carried out, a jitter of the output signal of the digital PLL circuit is still large.